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Cadence

Design Verification Engineer

Actively Reviewing

Cadence

Noida Full-Time 4–8 yrs exp Posted 2 days ago  · Apply by Sep 14, 2026

Job Summary

We are seeking a highly motivated candidate with expertise in functional verification, specifically focusing on Verification IP (VIP) development. The ideal candidate will be able to quickly and independently adapt to new technologies and protocols. Excellent communication skills are essential, as the role involves cross-functional collaboration and close interaction with customers.


Job Responsibilities

Responsible for the design, development, verification and deployment of the VIP.


Experience and Technical Skills required

  • 3- 6 years of design verification.
  • Proficiency in functional verification, test environment creation using SV/UVM with strong debug skills.
  • Hands-on knowledge of C/C++/Scripting.
  • Working experience on layered Protocols - PCIe, Ethernet, UCIe, CXL UAlink.
  • Prior VIP usage and development experience is a plus.
  • Strong Digital Electronics and Programming fundamentals.
  • Self-motivated individuals with strong analytical and communication skills.


C++